1. Field of the Invention
This invention relates to a semiconductor memory, and more particularly to a clock synchronous memory with a delay control circuit which controls the synchronism of a clock and input/output data.
2. Description of the Prior Art
Recently, the semiconductor memory has rapidly integrated. In addition to the high integration, the semiconductor memory requires a highly data access speed. An asynchronous system is used as a primary semiconductor memory. However, the asynchronous system limits the data access speed at the critical speed, and thus almost all of the recent semiconductor memories use a clock synchronous system.
The clock synchronous memory allows data to be accessed at super high speed. A synchronous DRAM (Direct Random Access Memory), a rambus DRAM and a synchronous link DRAM (hereinafter, SLDRAM) and so on, are commonly used as a clock synchronous memory. Particularly, the SLDRAM is known as a typical memory which performs data transmission in a packet system.
FIG. 1 is a block diagram showing the construction of a conventional SLDRAM system. The conventional SLDRAM system consists of a plurality of SLDRAMs 200-1 to 200-N and a memory controller 100 for controlling a data input/output operation of the plurality of SLDRAMs 200-1 to 200-N.
Next, the operation of the SLDRAM system shown in FIG. 1 will be described. In FIG. 1, the N SLDRAMs 200-1 to 200-N are commonly connected to the memory controller 100 by means of unidirectional command link which allows an unidirectional communication from the memory controller 100 toward each SLDRAM 200-1 to 200-N. Also, the SLDRAMs 200-1 to 200-N are commonly connected to the memory controller 100 through a bi-directional data link which performs a bi-directional communication between the memory controller 100 and each SLDRAM 200-1 to 200-N. Each SLDRAM 200-1 to 200-N receives the commands of a packet unit from the memory controller 100 through the command link and decodes the commands of the packet unit, thereby performing various operations such as a reading out, a writing and so on. The SLDRAMs receive or output data (read out data, data to be written, DCLK0 and DCLK1) through the data link. Actually, one command packet is applied to the SLDRAM 200 during a period of 4 ticks, and the data is output/applied from/to the SLDRAM 200 according to the command packet. Herein, the "tick" represents the half period of an operating frequency signal. For example, if the operating frequency signal is set up at a frequency of 300 MHz, the "tick" goes to 1.65 ns since one period of the operating frequency signal corresponds to 3.3 ns.
The SLDRAM 200 uses both the rising and falling edges of a clock. In other words, the data is output from the SLDRAM 200 each time the clock is toggled. Therefore, the quantity of the data responding to both the rising and falling edges of the clock is twice that of data responding to any one of the rising and falling edges of the clock. In the case of using a clock of 300 MHz, the data rate is 600 Mbit/s/p.
The following is a description for the operations wherein the data is transmitted between the memory controller 100 and the SLDRAM 200-1 to 200-N. When the data is read out from the SLDRAM 200-1 to 200-N, the SLDRAMs 200-1 to 200-N generate the clock DCLK and apply the clock DCLK with the read out data to the memory controller 100. Meanwhile, in the case of writing the data to the SLDRAMs 200-1 to 200-N, the memory controller 100 produces the clock DCLK and supplies the clock DCLK with the data to be written to the SLDRAMs 200-1 to 200-N.
However, in the case that SLDRAMs are arranged as shown in FIG. 1, each data transfer time is different from each other in the SLDRAMs 200-1 to 200-N when the data is transmitted between the memory controller 100 and each SLDRAM 200-1 to 200-N. A compensatory delay quantity is stored into a specific register in order for it to conform to the delay of the data, but the delay quantity stored into the specific register can differ from the delay quantity which is measured in reality. This results from an exterior factor, the load resistance of a signal line and so on. If the delay quantity differs, the transmission of the data may not be performed in an accurate timing. Also, a miss operation can be generated by the increase of the difference between the delay quantities.